LZ是北郵電子院研三的，現(xiàn)在在愛立信北京研發(fā)中心實(shí)習(xí)，因?yàn)闇?zhǔn)備找工作了，近期將離職。想內(nèi)推一位北郵同學(xué)來(lái)接替我的工作。老板是北郵畢業(yè)的，所以你們懂得……

我的部門主要是做CDMA產(chǎn)品的FPGA、CPLD設(shè)計(jì)與驗(yàn)證，部門的氛圍很好，人都很nice，能學(xué)到不少東西，如果你想在數(shù)字邏輯設(shè)計(jì)方面發(fā)展，來(lái)這錯(cuò)不了，不想做設(shè)計(jì)的也可以轉(zhuǎn)驗(yàn)證。

發(fā)一個(gè)正式員工的JD吧

Job Description for FPGA Design Engineer
Software Developer
Description:
• FPGA functional design with VHDL.
• FPGA simulation and verification strategy planning and architecture design.
• Feature point extraction and test case planning and design and debugging.
• Documentation for related tasks, also be responsible for document review, code inspection and other tasks required by quality process.
• Familiar with ClearCase.

Qualifications:
• More than 3 years working experience on FPGA design and verification in Telecommunication product field. [color=#0000FF]（這條可忽略）[/color]
• Good Knowledge on FPGA design process, procedure, knowledge on verification methodology, OVM is a plus
• Be familiar with standard HW protocol and interfaces and IO standards, SRIO, PCI, PCI-e, Local bus, SERDES, I2C, SGMII, Flash/SDRAM.
• Good understanding of IO timing, system/FPGA clocking, system/FPGA reset structure and strategy.
• Good sense of co-working with team members under ClearCase like source control environments is a plus.

其他要求：北郵剛上研二的學(xué)生（其他學(xué)校的同學(xué)抱歉了），能保證每周三、四天的出勤率，半年以上的實(shí)習(xí)期。老板說女生優(yōu)先考慮（team的男女比例很不協(xié)調(diào)）。專業(yè)能力見上，良好的數(shù)字邏輯設(shè)計(jì)、驗(yàn)證基礎(chǔ)是需要的，其他的可以去了學(xué)習(xí)。

待遇：愛立信研究生都是20rmb/h。

如果覺得合適，可以把你的簡(jiǎn)歷發(fā)給我：34827440@qq.com（內(nèi)部郵箱就不留了，怕廣告什么的），我將把簡(jiǎn)歷轉(zhuǎn)給我們的老板，謝謝。