Position: Freescale Design For Test Engineer ( For Intern )
Location: TEDA, Tianjin
Duration: Now ~ Dec. 31, 2014 ( Not a mandatory requirement, but longer is better. )
Qualification:
1. Bachelor, Master on Electronics, Communications, Microelectronics Engineering and Computer Science.
2. Basic logic design and verification background with debugging capability, Experience in digital design with good knowledge of SoC design flow, including RTL coding, simulation, synthesis, DFT and silicon test.
3. Familiar with industrial standard DFT methodology and tools, basic understanding of scan, ATPG, memory BIST, LBIST, T, Boundary scan, etc.
4. Knowledge in ATE and experience in silicon validation on tester will be a plus.
5. Nice to have skills: script language like perl, tcl.
Job Description:
1. Perform design implementation and verification on test modules, scan ion, test compression, Memory Build In Self Test, JTAG/Boundary scan.
2. Be responsible for improve the testability of IP and chip to meet test coverage requirement.
3. Be responsible for scan pattern generation, BIST and boundary scan pattern generation and verification.
4. Be responsible for test time reduction research.
Contacts: r61918@freescale.com
